An Improved Architecture for Optimizing Partitioning Cost of Time-Multiplexed FPGA

Y.-T. Lai, T.-C. Tai, C.-C. Kao, and C.-K. Liu (Taiwan)


TMFPGA, architecture, partition, precedence constraint, and circuit


The Time-Multiplexed FPGA (TMFPGA) dramatically improves logic utilization by using time-sharing logic. In order to use TMFPGA, the precedence constraints must be followed. It is a problem with high partitioning cost to partition a circuit for implementation on a TMFPGA. In this paper, we present a new TMFPGA architecture to simplify the precedence constraints such that the minimum partitioning cost of Time-Multiplexed FPGA problem can be optimized. This is achieved by applying the same clock signal to both the flip-flop and micro register inside control logic block (CLB). They are directly accessible from outside CLB by adding two multiplexers. For execution efficiency, a control signal is added to select the desired reconfiguration memory plane. To show the effectiveness of the new architecture, we implement an example circuit on the new TMFPGA.

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