A Performance Model for Network Processor Architectures in Packet Processing System

M. Ahmadi and S. Wong (The Netherlands)


Network processors, queuing theory, Jack son network, bandwidth limitation


Network processors (NPs) are designed to provide both performance and flexibility through the implementation of both parallel and programmable architectures. Typically, such processors encompass a parallel processor core with several memories and specialized co-processors. A com mon task performed by such processors is packet process ing that is both complex and highly repetitive. Conse quently, the challenge is to define an on-chip network pro cessor architecture that is capable of meeting the perfor mance requirements of packet processing. With the current technological advances, it is expected that many (network) processor cores are to be incorporated onto the same chip to perform packet processing for which an efficient configu ration must be determined. In this paper, we propose a gen eral framework for analyzing the performance of a network processor that consists of an (on-chip) network of NPs. For this purpose, we utilize queuing theory to model the pro posed network processor and analyze it. More specifically, the Jackson network model is utilized to represent our net work processor. The simulation results show that the pro posed network processor is able to improve the response time and throughput when compared to a more traditional network processor.

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