Fast VBSME Design using Reconfigurable Hardware Architecture and Search Range Reduction Algorithm

Y. Fan, T. Ikenaga, and S. Goto (Japan)


Fast VBSME, Search Range Reduction, Reconfigurable Architecture


This paper proposes a fast VBSME design which using a Hardware-oriented Search Range Reduction (H-SRR) algorithm and a reconfigurable hardware architecture. The proposed H-SRR algorithm can reduce the computational complexity to less than 10% of fast full search algorithm almost without PSNR degradation. The proposed reconfigurable hardware architecture can be dynamically configured according to the new search range shape. It achieves 100% hardware utilization while working with proposed H-SRR algorithm. Using TSMC 0.18μm standard cell library, the implementation results show that the hardware cost of design which uses 16 PEGs (PE Groups) is about 190 K Gates, the clock frequency is 243 MHz.

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