A Multi-Scenarios TLM Performance Analysis for On-Chip Communication Structure Design

S. Eslava, J.C. Wang, and M. Strum (Brazil)


System-on-Chip, System Level Design, Performance Analysis, On-chip Communication Structure, Transaction Level Modeling.


Complex System-on-Chip (SoC) designs require several methodologies in order to handle their growing complexity. On-Chip communication structure design is a very difficult task. It can be performed through a gradual refinement strategy using different high abstraction levels (like TLM) or at the low abstraction RTL level. This task is affected by a set of huge parameters and constraints, including: the number of hardware/software elements and the workload conditions. In this paper, an enhanced analysis technique is presented that improves a previous CS design methodology. The proposal identifies several system operating conditions and includes them at the parameter configuration. This allows finding a solution that can be adequate under the different operating conditions. The application used is an internet protocol (IP) router configured as a multi-master system.

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