Comparison of Voltage Scaling and Gate Sizing for Low-Power Custom IC Design

T. Goksu (Turkey) and A. Manzak (Canada)


VLSI circuits, power management, gate sizing, voltage scaling.


This paper compares two low power design methods, the voltage scaling and the gate sizing for custom designed cir cuits. We minimize power consumption subject to a tim ing constraint and compare effectiveness of voltage scal ing and gate sizing for low power. We apply both low power methods to custom designed adders, multipliers and buffer chain. Each circuit is carefully sized and simulated for given latencies. The results are compared in terms of power and area. Experiments show that gate sizing is more effective than voltage scaling for all the custom circuits we have designed and simulated for power reduction. Gate siz ing also has the advantage of reduced silicon area. We have concluded that the custom designer should first choose gate sizing for a low power design method. If more latency is available, voltage scaling can be considered as an ad ditional step for further power reduction.

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