A Fast and Parallel Hardware Architecture for Variable Block Size Motion Estimation in H.264/AVC

W. Jin and C.N. Zhang (Canada)


VLSI Circuits and Systems, Motion Estimation, Variable Block Size, H.264/AVC, Parallel Hardware Architecture


The new video standard H.264 adopts variable block size motion estimation (VBSME), which supports more flexibility and provides more accuracy in the process of selecting the best matching position of a macroblock of the current frame within a search window in the previous frame. However, for the full-search matching algorithm that has the best performance, it requires considerable and much more complicated computation than fixed block size motion estimation adopted in previous standard such as MPEG-2. Hence hardware implementation is necessary for the real time applications. A parallel hardware architecture for VBSME is presented, featured in a fast computation circuit for computing the absolute difference of one pixel, a delicately designed carried save adder tree for computing the summation of absolute difference (SAD) of one 4x4 block, the parallel computation and combination of variable block size SAD and the data feeding mechanism. The implementation result shows that the architecture can generate 41 SADs for one macroblock in 5 clock cycles and the pipeline period is 1 clock cycle. The hardware cost is 146K gates and the maximum working frequency is 115 MHz.

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