A VGA 30 FPS Affine Motion Estimation Processor for Real-Time Video Segmentation

Y. Yunbe, M. Miyama, and Y. Matsuda (Japan)

Keywords

Affine motion model, realtime, video segmentation, VLSI, and FPGA

Abstract

This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo M-estimator algorithm. Introduction of a binary weight method and an image division method to the original algorithm reduces data traffic and hardware costs. In addition, a pixel sampling method can reduce the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The proposed VLSI architecture can accommodate a VGA 30-fps video with 120 MHz clock frequency. The processor was implemented prototypically on an FPGA; its function and performance were subsequently verified. The estimated core size is 13.15 mm2 with 0.18-┬Ám process, standard cell technology.

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