A 7.8 GHz CMOS Phase Locked Loop

S. Ren and R. Siferd (USA)


PLL, VCO, CMOS, Dual Delay


A high frequency Phase Locked Loop (PLL) incorporating a Voltage Controlled Oscillator (VCO) with a dual delay architecture is presented. Schematic and layout designs in 180 nm CMOS technology are included together with fabrication and test results. The VCO employs four dual delay cells to produce stable and accurate in phase and quadrature clock sources with a wide tuning range and low phase noise. The schematic simulation results show that the PLL can achieve lock with the VCO frequency as high as 7.8 GHz. Designs are presented for PLL center frequencies of 2.0 GHz and 7.8 GHz.

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