Simulation of Level-2 Cache Locking in Multicore Parallel Computing Systems

M. Rani, A. Asaduzzaman, and D. Koivisto (USA)


Multicore architecture, level-2 cache locking, system performance, execution time predictability


In order to fulfill the demands for increased performance / power ratio, most chip-vendors are deploying multicore processors to their product lines. Multicore processors are frequently deployed with multilevel cache memories. Parallel thread execution in such a multicore system is difficult as it relates to cache sharing to achieve the best performance. Due to the increased execution time unpredictability, it becomes a challenge to support real time applications on multicore systems with multilevel caches. Studies show that predictability can be improved using cache locking techniques. However, entire locking at level-1 cache may be inefficient for smaller data size (when compared with the cache size). Also, way locking at level-1 cache is not permitted on some processors (like PowerPC 750GX), but way locking at level-2 cache is possible. By locking at level-2 cache, Xenon processor achieves the effect of using local storage by Cell SPEs. In this work, we simulate a multicore parallel computing system with two levels of caches to explore the impact of level-2 cache locking on the performance, power consumption, and predictability. Experimental results show that performance and predictability can be increased and power consumption can be decreased by adding a level-2 cache locking mechanism to an efficient cache sharing structure.

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