Development of a Network on Chip for Parallel Processing Systems

K. Tanaka, S. Iwanami, T. Ohashi, T. Yamakawa, and C. Fukunaga (Japan)


Parallel Processing, Parallel Programming, Routing, Interconnection Network


We have developed a network (called TPNET) which is adaptable for any parallel processing systems. It consists of several core processors and a router. A process element in a parallel processing system is a processor called TPCORE2, which has been developed by the authors’ group. Since this core processor can execute full set of the transputer instruction set, we can describe a software system using the parallel processing language occam. Occam is based on theoretically a model called Communicating Sequential Processes (CSP). If a parallel system can be described in occam language, and work fine, it will be regarded as free from any deadlocks or livelocks which will be intrinsically hidden in a parallel system. We can construct simply a secure parallel processing system in this way. Each processor can be connected to a router, and we can achieve a dynamic configuration of the network topology by controlling the router. The basic communication protocol in TPNET is IEEE 1355. An assured and efficient network can be constructed despite the structural simplicity of the protocol. With characteristics discussed above and with an efficient interrupt processing system in TPCORE2, we propose this TPNET as a basic framework for high performance embedded systems used widely in various industrial fields.

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