Efficient Parallel Architecture of Median Filter

R. Medhat, H.M. Faheem, and M.E. Khaleefa (Egypt)


Median Filter, VHDL, Parallel Architecture


Many attempts have been made to optimize the median filter from the software and hardware approach. An architectural design of hardware capable of performing real-time median filtering is presented. The architecture uses the histogram approach to calculate the median, while optimizing the sliding window method to reuse all its calculations. Data is output row by row and every input pixel is processed only once. The design is independent of window size or image size, and supports adding more processing elements to support wider images. The control unit design is minimized to enable self-adjustment of plug and-play processing elements. The architecture is implemented in VHDL and synthesized to a Virtex-2 Pro FPGA. The architecture’s performance as well as operation is compared to previous work.

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