e-Infrastructure Support for nanoCMOS Device and Circuit Simulations

R.O. Sinnott, G. Stewart, A. Asenov, C. Millar, D. Reid, G. Roy, S. Roy, C. Davenhall,B. Harbulot, and M. Jones (UK)


nanoCMOS electronics, high performance computing, data management, security.


The UK e-Science EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS – www.nanocmos.ac.uk) was funded to address the challenges facing the global electronics semiconductor industry caused by the decreasing size of Complementary Metal Oxide Semiconductor (CMOS) transistors and the atomic variability present in devices manifest at these dimensions. Fundamental problems to be addressed include the modelling, understanding and predicting the effect of differences in the atomic structure of devices on their behaviour, and then using this information to guide electronic circuit and system designers who utilise CMOS components. In this paper we describe the e-Infrastructure that has been developed as part of the nanoCMOS project and outline how it supports large scale high performance computing (HPC) simulations of ensembles of devices which can subsequently be used to model and understand the impact that they have on very large electronic circuits. Key features of this e-Infrastructure include support for very large scale HPC utilization; dealing with federated data sets and associated metadata from multi-level simulations, and addressing challenges related to security and intellectual property protection of data, simulation codes and electronic designs as a whole.

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