A Simplified Architecture for the Implementation of Viterbi Algorithm

S.Y. Ameen (Bahrain), A.K. Al-Sulifany, and M.H. Al-Jammas (Iraq)


Viterbi Decoder, FPGA Implementation, Low Power Digital Receivers.


The paper presents the design and the implementation of simple Viterbi decoder architecture, where a set of transformation techniques are applied. These techniques include reducing the operation, new algorithms for comparison, fast decision of correct path, and generating the original output sequences based on the survivor path. Furthermore, a low power design of Viterbi decoders have been achieved by reducing the decoder elements with new algorithm. The decoder has been designed to work in wireless communications applications and in mobile phone for different rates have been proposed by finding the correct paths directly. The proposed decoder has been investigated and assessed at high frequency. Next, the proposed decoder has been implemented using FPGA. The experimental results show that, the proposed design can be represented with many elements of gates and Flip Flops and can be work at high clock frequency. Furthermore, the proposed architecture can be used to realize a Viterbi decoder which can support constraint length 7 and 9 and rates 1/2 and 1/3.

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