Thread-Level Automatic Parallelization in the Elbrus Optimizing Compiler

L. Mukhanov, P. Ilyin, A. Ermolitsky, A. Grabezhnoy, S. Shlykov, and A. Breger (Russia)


Automatic parallelization, TLP, EPIC, optimizing compiler


Most microprocessor manufacturers are currently moving toward multi-core and multiprocessing systems, because it is becoming very difficult to increase the performance of a single-core microprocessor. To enjoy the advantages of multi-core and multiprocessing systems in applications, software engineers must redesign these applications with appropriate tools. For some applications, such redesign could be very complex and thus expensive. As a result, most microprocessor manufacturers are trying to develop thread-level automatic parallelization functionality in their optimizing compilers. Such compilers allow application developers to enjoy all the advantages of multi-core and multiprocessing systems without redesigning their applica tions. In this paper, we discuss automatic parallelization in the Elbrus (EPIC architecture) optimizing compiler. We describe thread-level automatic parallelization for EPIC ar chitectures in detail, as well as the automatic parallelization techniques we developed and the results of our tests.

Important Links:

Go Back