Implementation of Multithread Processors for Packet Processing

K. Li, Q. Wang, P. Ma, J. Shi, Y. Wang, and P. Liu (PRC)


Computer network, IP network, multithreading´╝îchip multiprocessors, performance


Research of the architecture of multithreaded chip multi processor (CMP) with throughput-oriented optimization is an important domain on performance of the network processors. To enhance processing performance of the network processors, the multithreaded application-specific instruction processor (ASIP) core with the blocked multithreading (BMT) architecture and a static Round Robin thread arbitration policy was designed. The processor core adopts a packet-optimized instruction set and utilizes a 5-stage pipelining RISC processor as its baseline architecture. This multithread architecture not only decreases hardware context-switch overhead up to zero or one cycle, but guarantee executive fairness among the several threads at the same time. The processor was implemented on the FPGA platform of Xilinx Virtex-II PRO xc2vp30. The verification result shows the multithreaded core has 3 times the performance of the baseline structure, while chip area increases only 7%. So the multithreaded processors update from baseline can easily implemented as well as acquire remarkable improvement on processing capability of IP network and access device.

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