Test Response Compaction in VLSI BIST with Array of Two-Input Linear Logic

Sunil R. Das and Alexander R. Applegate

Keywords

Aliasingfree space compaction, builtin selftesting in very large scale integration

Abstract

The design of aliasing-free space compactor for built-in self-testing of very large scale integration circuits and systems is of great importance, especially due to the design paradigm shift in recent years from system-on-board to system-on-chip. The subject paper further investigates and provides additional results on a recently developed approach to designing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, extending well known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incomplete sequential machines. For a pair of response outputs of the circuit under test, this method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input XOR/XNOR linear logic. The process is illustrated with design details of space compactors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA and FSIM, demonstrating the importance of the technique from the viewpoint of simplicity, resulting low area overhead and full fault coverage for single stuck-line faults, thereby making it an appropriate choice in practical design environments.

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