Design of a Reconfigurable Pipelined Switch for Faulty On-Chip Networks

Hsin-Chou Chi and Tat-Seng Chang


network-on-chip architectures, routing switches, network routing algorithm, fault tolerance


Network-on-chip (NoC) architectures have been recently proposed as the communication framework for large-scale chips. The design of the routing system for the packet-switched on-chip network is one of the critical issues for the success of NoC architectures. In this paper, we present the design of a reconfigurable pipelined switch for mesh on-chip networks. When the switch is in the regular mode for the regular mesh, the routing is equivalent to the XY routing. When there are faulty links or switches, the switch is reconfigured in irregular mode for faulty mesh networks. The routing decision hardware in the switch is efficiently implemented based on a simple distance calculation algorithm. Our switch design is validated by implementation of four different versions with 64-bit, 128-bit, 256-bit, and 512-bit links, respectively. Our results show that our routing decision can be efficiently realized with distance calculation hardware.

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