Execution Environment on FPGA for Smart PC Hetero-Cluster

Kiyoshi Hayakawa and Keita Ito


Heterogeneous Computing, FPGA, Low Power Consumption, Application Specific Instruction set Processor


FPGAs tend to consume electric power in tens of milliwatts, and the ability to parallelize the applications on FPGAs results in increased performance-to-power-efficiency of FPGAs. FPGAs embedded into the computer cluster systems have been proposed. Smart cluster systems which control own power by themselves also have been proposed. For smart cluster systems, it is important to reduce CO2. Therefore, it is necessary to level power consumption in the entire facility to use the electric power effectively. Then, smart cluster systems are able to change the number of compute nodes including FPGAs dynamically by the power consumption of entire facility to level the total power consumption of the cluster system and other electronic devices. In this paper, we will propose an execution environment on FPGA for smart PC hetero cluster called SPHC. The FPGA calculation device is constructed by using the ASIP, Application Specific Instruction set Processor on the FPGA. In preliminary evaluation, we compared a MAC (or F) processor and a normal processor. And we achieved 60.7MFLOPS/W on FDTD.

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