A Power-Aware Versatile Victim Cache to Reduce Average Memory Latency in Parallel Architectures

Abu Asaduzzaman, Rowshon J. Papri, and Mizan Rahman


Cache memory subsystem, Memory latency, Parallel architecture, Total power consumption, Victim cache


In recent times, power consumption and heat dissipation have become crucial for designing parallel computer architecture. Multi-level cache memory organization in multiprocessor/multicore system increases total power consumption as cache is very power hungry. Studies suggest that there are realistic opportunities to increase performance/power ratio of parallel architectures by rearranging and multi-using its cache memory organization. In this paper, we propose a novel approach to reduce the total power consumption and mean memory latency of multicore systems by introducing a versatile victim cache (VVC). In addition to functioning as a regular victim cache, proposed VVC holds block address and miss information (BAMI) entries, supports stream buffering, and entirely eliminates the need of cache locking. We simulate a quad-core system that has private level-1 cache (CL1), shared level-2 cache (CL2), VVC in between CL1s and CL2, and the main memory. We run the simulation programs using popular multimedia workloads including MPEG-4 and H.264/AVC. Experimental results show that the quad-core system with proposed VVC decreases the mean memory latency and total power consumption by up to 38% and 31%, respectively, when compared with a CL2 cache locking system without VVC.

Important Links:

Go Back