A PC-CLUSTER-BASED FULLY DIGITAL REAL-TIME SIMULATION OF A FIELD-ORIENTED SPEED CONTROLLER FOR AN INDUCTION MOTOR

M. Ouhrouche, R. Beguenane, A.M. Trzynadlowski, J.S. Thongam, and M. Dub´-Dallaire

References

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  15. [15] J. Chiasson & L. Tolbert, A library of Simulink blocks for real-time control of HEV traction drives, Proc. Future Car Congress, Arlington, VA, June 3–5, 2002, 30–41. Appendix A: List of Symbols Vsd, Vsq: stator voltages in the synchronously rotating reference frame Isd, Isq: stator currents in the synchronously rotating reference frame ψrd, ψrq: rotor fluxes in the synchronously rotating reference frame Vsα, Vsβ: stator voltages in the stationary reference frame Isα, Isβ: stator currents in the stationary reference frame ψrα, ψrβ: rotor fluxes in the stationary reference frame ωr: rotor speed (rad/s) ωe: synchronous speed (rad/s) Rs, Ls: stator resistance and self inductance Rr, Lr: rotor resistance and self inductance. Lm: magnetic inductance p: number of pole pairs J: total rotor inertia constant (kg · m2 ) F: damping coefficient (N · m · s) Tl: load torque (N · m) Appendix B: Real-Time Models Implementation in RT-Lab Environment Figs. B1–B4 shows the details of the four block diagrams—respectively SS_CONTROLLERS, SS_INV_ MOTOR, SM_BREAKOUT_BOX, and SC_USER_ INTERFACE—used for IFOC implementation using RTLab simulator as shown in Fig. 6. These block diagrams are actually Simulink models grouped to form a subsystem. Figure B1. Details of the slave #1 (SS_CONTROLLERS) block diagram. 226 Figure B2. Details of the Slave #2 (SS_INV_MOTOR) block diagram. Figure B3. Details of the master (SM_BREAKOUT_ BOX) block diagram. Figure B4. Details of the console (SC_USER_INTERFACE) block diagram. Once the models are grouped into console (SC_), data acquisition (SM_), and computation (SS_) subsystems, special blocks called OpComm blocks must be inserted into the subsystems [6]. These are simple feed-through blocks that intercept all incoming signals before sending them to computation blocks and provide information to RT-Lab concerning the type and size of these intercepted signals. This signal interception is mandatory because when a simulation model runs in the RT-Lab environment, all connections between the main subsystems are replaced by hardware communication links. Memory blocks are added in each subsystem in order to take into account delays that might occur during information exchange.

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