TESTABLE DESIGN OF DIGITAL SUMMATION THRESHOLD LOGIC ARRAY FOR SYNTHESIS OF SYMMETRIC FUNCTIONS

H. Rahaman, D.K. Das, and B.B. Bhattacharya

References

  1. [1] S.L. Hurst, Digital summation threshold logic gates: A new circuit element, IEE Proc., 120(11), 1973, 1301–1307.
  2. [2] W. Ke & P.R. Menon, Delay-testable implementations of symmetric functions, IEEE Trans. on CAD, 14, 1995, 772–775.
  3. [3] S. Chakraborty, S. Das, D.K. Das, & B.B. Bhattacharya, Synthesis of symmetric functions for path-delay fault testability, IEEE Trans. on CAD, 19, 2000, 1076–1081.
  4. [4] Z. Kohavi, Switching and finite automata theory (New York: McGraw-Hill, 1977).
  5. [5] J. Ja Ja & S.M. Wu, A new approach to realize partially symmetric functions, Technical Report SRC TR 86–54, Department of Electrical Engineering, University of Maryland, 1986.
  6. [6] H. Rahaman, D.K. Das, & B.B. Bhattacharya, A new synthesis of symmetric functions, Proc. Joint Int. Conf. on ASP-DAC and VLSI Design, January 2002, 160–165.
  7. [7] D.L. Dietmeyer, Generating minimal covers of symmetric function, IEEE Trans. on CAD, 12(5), 1993, 710–713.
  8. [8] J. Shi, G. Fey, & R. Drechsler, BDD based synthesis of symmetric functions with full path-delay fault testability, Proc. of Asian Test Symp., 2003 (ATS03), 290–293.
  9. [9] Y.X. Yang & B. Guo, Further enumerating Boolean functions of cryptographic significance, Journal Cryptology, 8(3) 1995, 115–122.
  10. [10] A. Pal & B.B. Bhattacharya, Syndrome-testable logic design using DSTL arrays for detecting stuck-at and bridging faults, IEE Proc. of Computers and Digital Techniques, Part E, 132(5), 1985, 251–256.
  11. [11] R.J. Tocci & N.S. Widmer, Digital systems principles and applications (Pearson Education Asia, 2001).
  12. [12] E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, et al., SIS: A sequential system for sequential circuit synthesis, Technical Report UCB/ERL m92/41, Electronic Research Laboratory, University of California, Berkley, CA, May 1992.
  13. [13] H. Rahaman, D.K. Das, & B.B. Bhattacharya, Implementing symmetric functions with hierarchical modules for stuck-at and path-delay fault testability, Journal of Electronic Testing— Theory and Applications (JETTA), 22(2), 2006, 125–142. doi:10.1007/s10836-006-6674-3

Important Links:

Go Back