CONCURRENT BIST SYNTHESIS AND TEST SCHEDULING USING GENETIC ALGORITHMS

H.M. Harmanani and A.M.K. Ha jar

References

  1. [1] G. De Micheli, Synthesis and optimization of digital circuits (New York: McGraw Hill, 1994).
  2. [2] M.L. Bushnell & V.D. Agrawal, Essentials of electronic testing for digital, memory, and mixed signal VLSI circuits (Boston: Kluwer Academic Publishers, 2000).
  3. [3] C.E. Stroud, A designer’s guide to built-in self-test (Boston: Kluwer Academic Publishers, 2002).
  4. [4] B. Koenemann, J. Mucha, & G. Zwiehoff, Built-in logic block observation techniques, Proc. of the Int. Test Conf., Cherry Hill, NJ, October 1979, 37–41.
  5. [5] I. Parulkar, S. Gupta, & M. Breuer, Scheduling and module assignment for reducing BIST resources, Proc. DATE 98.
  6. [6] A.E. Eiben & J.E. Smith, Introduction to evolutionary computing (Berlin: Springer-Verlag, 2003).
  7. [7] K. Wagner & S. Dey, High-level synthesis for testability: A survey and perspective, Las Vegas, Nevada, Proc. DAC, 1996, 131–136.
  8. [8] C. Papachristou, S. Chiu, & H. Harmanani, A data path synthesis method for self-testable designs, Proc. of the 28th Design Automation Conf., San Francisco, CA, June 1991, 378–384.
  9. [9] C. Papachristou, S. Chiu, & H. Harmanani, SYNTEST: A method for high-level synthesis with self-testability, Proc. Int. Conf. on Computer Design, Cambridge, MA, 1991, 458–462. doi:10.1109/ICCD.1991.139947
  10. [10] H. Harmanani & C. Papachristou, An improved method for RTL synthesis with testability trade-offs, Proc. ICCAD, Santa Clara, CA, 1993.
  11. [11] L. Avra, Allocation and assignment in high-level synthesis for self-testable data paths, Proc. ITC, Nashville, TN, 1991.
  12. [12] I. Parulkar, S. Gupta, & M. Breuer, Allocation techniques for reducing BIST overhead of datapaths, Journal of Electronic Testing & Theory Application, 13, 1998, 149–166. doi:10.1023/A:1008357805049
  13. [13] K. Olcoz, F. Tirado, & H. Mecha, Unified data path allocation and BIST intrusion, Integration, the VLSI Journal, 28, 1999, 55–99.
  14. [14] M. Zwolinski & M. Gaur, Integrating testability with design space exploaration, Microelectronics Reliability, 43, 2003, 685–693. doi:10.1016/S0026-2714(03)00034-9
  15. [15] G. Craig, C. Kime, & K. Saluja, Test scheduling and control for VLSI built-in self-test, IEEE Trans. on Computers, C-37, 1988, 1099–1109. doi:10.1109/12.2260
  16. [16] I. Harris & A. Orailoglu, SYNCBIST: Synthesis for concurrent built-in self-testability, Proc. EDTC, Cambridge, MA, 1994, 101–104.
  17. [17] H. Kim, T. Takahashi, & D. Ha, Test session oriented built-in self-testable data path synthesis, Proc. Int. Test Conf., Washington, DC, October 1998, 154–163.
  18. [18] H. Kim, D. Ha, T. Takahashi, & T. Yamaguchi, A new approach to built-in self-testable datapath synthesis based on ILP, IEEE Trans. on VLSI, 8, 2000, 594–605. doi:10.1109/92.894164
  19. [19] M. Dhodhi, F. Hielscher, R. Storer, & J. Bhasker, Datapath synthesis using a problem-space genetic algorithm, IEEE Trans. on CAD, 14, 1995, 934–944.
  20. [20] L.T. Wang & E.J. McCluskey, Concurrent built-in logic block observer, Proc. ISCAS’86, San Jose, CA, 1986, 1054–1057.
  21. [21] P. Bukovjan, L. Ducerf-Bourbon, & M. Marzouki, Cost/quality trade-off in synthesis for BIST, JETTA, 17, 2001, 109–119.

Important Links:

Go Back