Hussein R. Al-Zoubi, Anas M. Bataineh, and Osama D. Al-Khaleel


  1. [1] H.-S. Hong, H.-K. Lee, H.-S. Lee, and H.-J. Lee, The betterbound of private key in RSA with unbalanced primes, AppliedMathematics and Computation, 139, 2003, 351–362.
  2. [2] S. Deng, Y. Li, and D. Xiao, Analysis and improvement ofa chaos-based hash function construction, Communicationsin Nonlinear Science and Numerical Simulation, 15, 2010,1338–1347.
  3. [3] M. Thaduri, S.M. Yoo, and R. Gaede, An efficient VLSIimplementation of IDEA encryption algorithm using VHDL,Microprocessors and Microsystems, 29, 2005, 1–7.
  4. [4] Y. Rezgui and A. Marks, Information security awareness inhigher education: An exploratory study, Computers & Security,27, 2008, 241–253.
  5. [5] M.T. Dlamini, J.H.P. Eloff, and M.M. Eloff, Informationsecurity: The moving target, Computers & Security, 28, 2009,189–198.
  6. [6] S. Mhlbach and S. Wallner, Secure communication in mi-crocomputer bus systems for embedded devices, Journal ofSystems Architecture, 54, 2008, 1065–1076.
  7. [7] G.P. Saggese, L. Romano, N. Mazzocca, and A. Mazzeo, Atamper resistant hardware accelerator for RSA cryptographicapplications, Journal of Systems Architecture, 50, 2004, 711–727.
  8. [8] M. Long, Implementing skein hash function on xilinx virtex-5FPGA platform, Intel Corporation, 7, 2009, 1–15.
  9. [9] A.J. Acosta, E.J. Peralias, A. Rueda, and J.L. Huertas, VHDLbehavioral modeling of pipeline analog to digital converters,Measurement, 31, 2002, 47–60.
  10. [10] D. Gil, J. Gracia, J.C. Baraza, and P.J. Gil, Study, compar-ison and application of different VHDL-based fault injectiontechniques for the experimental validation of a fault-tolerantsystem, Microelectronics Journal, 34, 2003, 41–51.
  11. [11] A. Amara, F. Amiel, and T. Ea, FPGA vs asic for low powerapplications, Microelectronics Journal, 37, 2006, 669–677.
  12. [12] J.C. Baraza, J. Gracia, D. Gil, and P.J. Gil, A prototype of aVHDL-based fault injection tool: Description and application,Journal of Systems Architecture, 47, 2002, 847–867.
  13. [13] D. Shaw, D. Al-Khalili, and C. Rozon, Fault security analysisof CMOS VLSI circuits using defect-injectable VHDL models,Integration, the VLSI journal, 32, 2002, 77–97.
  14. [14] G. Asadi, S.G. Miremadi, and A. Ejlali, Fast co-verification ofHDL models, Microelectronic Engineering, 84, 2007, 218–228.
  15. [15] G.Ch. Sirakoulis, I. Karafyllidis, and A. Thanailakis, A CADsystem for the construction and VLSI implementation of Cel-lular Automata algorithms using VHDL, Microprocessors andMicrosystems, 27, 2003, 381–396.
  16. [16] V. Jannepally, Bus encryption and authentication unit forsymmetric shared memory multiprocessor system using GCM-AES, Master’s thesis, Department of Electrical Engineering,Oklahoma State University, OK, USA, 2009.
  17. [17] O.B. Adamo, VLSI architecture and FPGA prototyping of asecure digital camera for biometric application, Master’s thesis,132Department of Electrical Engineering and Computer Science,University of North Texas, TX, USA, 2007.
  18. [18] S.R. O’Melia, Instruction set extension for enhancing the per-formance of symmetric key cryptographic algorithms, Master’sthesis, Department of Electrical Engineering and ComputerScience, University of Massachusetts, Lowell, MA, USA, 2008.
  19. [19] F.-X. Standaert, G. Piret, G. Rouvroy, and J.-J. Quisquater,FPGA implementations of the iceberg block cipher, Integration,the VLSI Journal, 40, 2007, 20–27.
  20. [20] M. Ernst, B. Henhapl, S. Klupsch, and S. Huss, FPGA basedhardware acceleration for elliptic curve public key cryptosys-tems, The Journal of Systems and Software, 70, 2004, 299–313.
  21. [21] C. Chitu and M. Glesner, An FPGA implementation of theAES-Rijndaelin OCB/ECB modes of operation, Microelectron-ics Journal, 36, 2005, 139–146.
  22. [22] A. Cilardo, A. Mazzeo, L. Romano, and G.P. Saggese, Exploringthe design-space for FPGA-based implementation of RSA,Microprocessors and Microsystems, 28, 2004, 183-191.
  23. [23] J.M. Granado, M.A. Vega-Rodr´ıguez, J.M. S´anchez-P´erez, andJ.A. Go´omez-Pulido, IDEA and AES, two cryptographic algo-rithms implemented using partial and dynamic reconfiguration,Microelectronics Journal, 40, 2009, 1032–1040.
  24. [24] N. Ferguson, D. Whiting, B. Schneier, J. Kelsey, S. Lucks,and T. Kohno, Helix – fast encryption and authentication in asingle cryptographic primitive, in T. Johansson (ed.) Proc. FastSoftware Encryption 2003, volume 2887 of LNCS, (Sweden,Germany: Springer-Verlag, 2003), 330–346.
  25. [25] N. Ferguson, S. Lucks, B. Schneier, D. Whiting, M. Bellare,T. Kohno, J. Callas, and J. Walker, The Skein Hash FunctionFamily, Submission to NIST (Round 2), 2009.
  26. [26] S. Tillich, M. Feldhofer, M. Kirschbaum, T. Plos, J.-M.Schmidt, and A. Szekely, High-speed hardware implementa-tions of blake, blue midnight wish, cubehash, echo, fugue,grøstl, hamsi, jh, keccak, luffa, shabal, shavite-3, simd, andskein, Cryptology ePrint Archive, Report 2009/510, October2009.
  27. [27] A.H. Namin and M.A. Hasan, Implementation of the compres-sion function for selected sha-3 candidates on fpga, in work-shops and Ph.D. forum (IPDPSW), 2010 IEEE InternationalSymposium on Parallel distributed processing, April 2010, 1–4.
  28. [28] S. Tillich, Hardware implementation of the SHA-3 candidateskein, Cryptology ePrint Archive, Report 2009/159, April 2009.
  29. [29] Xilinx, Virtex-5 Family Overview.

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