A Fast Iterative Tap Amplitude and Delay Estimator Design for WCDMA

A. Burnic, T. Faber, T. Scholand, A. Waadt, and P. Jung (Germany)


Tap Amplitude and Delay Estimation (TADE); DSP (Digital Signal Processor); Implementation Aspects; Searcher, WCDMA (Wideband Code Division Multiple Access)


This communication discusses implementation aspects of a novel fast iterative tap amplitude and delay estimation (ITADE) technique for RAKE receivers required for the downlink in the UMTS (Universal Mobile Telecom munications System) FDD (Frequency Domain Duplex) mode WCDMA (Wideband Code Division Multiple Access). The Texas Instruments TMS320C6416 DSP (Digital Signal Processor), operating at 720 MHz clock rate, is taken as the target hardware. The manuscript shall primarily focus on a sliding correlation based ITADE algorithm developed by the authors. This algorithm shall be abbreviated by CITADE. The implementation of the CITADE algorithm exploits both the hierarchical structure of the primary synchronization channel (PSC) code, which is used as a reference for the TADE strategy, and the tailored instructions of the TMS320C6416 DSP. The found implementation requires 809 kcycles or, equivalently, 1.1 ms≈ of processing time. This processing time corresponds to the duration of 1.7 time slots≈ . The demand on computational power of the discussed CITADE algorithm is smaller by a factor of approx. 3.6 than the minimum requirements of the algorithm presented in [11], which was implemented on StarCoreTM SC140 DSP.

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