1.2V 300MHz CMOS PLL for Clock Generation in 0.35UM Process

D. McDonagh (UK), K.I. Arshak, and O. Abubaker (Ireland)


Phase locked loop, frequency synthesizer, clock generation, wideband PLL, VCO Figure 1 illustrates the block diagram of the PLL. The PLL contains a new phase/frequency detector (PFD), a drain-switching charge pump with voltage boost, an integrated loop filter and a new pseudo-differential voltage controller oscillator (VCO). This PLL runs from a single 1.2V supply/battery. The power supply for the charge pump needs to be boosted to 2.2V in order to achieve the 300MHz output frequency fr


This work describes a 1.2V low jitter PLL with wide frequency range for clock generation designed in a 3V 0.35um CMOS process. The phase frequency detector uses a new structure to extend the operating range. The charge pump uses input regulated mirrors to extend the output compliance range. The VCO is a pseudo differential buffer ring oscillator working up to 300MHz. In this paper, a 1.2V 0.35um CMOS PLL with a wide frequency range for clock generation systems is presented. A new full swing PFD has been designed to extend the operating frequency range. The charge pump is a drain switching circuit with high compliance regulated input cascode current mirrors. A voltage booster is used to supply the charge pump and extend its output voltage range. The oscillator is a full swing pseudo-differential CMOS ring structure. The typical oscillator tuning range is 30 to 300MHz. Cycle-to-cycle jitter due to a 100mV VDD variation (pk-pk) was 45ps. The current consumption of the PLL is 537uA at 300MHz. Section 2 gives a brief description of the PLL system. Section 3 details the circuits used in this PLL. Section 4 discusses the simulated results obtained. Finally, section 5 presents the conclusions. 2. System Description

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