H. Al-Asaad


  1. [1] H. Al-Asaad, EGFC: An exact global fault collapsing tool forcombinational circuits,Proceedings of the IASTED conferenceon Circuits, Signals, and Systems, 2005, 56–61.
  2. [2] H. Al-Asaad, AGFC: An approximate simulation-based globalfault collapsing tool for combinational circuits, Proceedings ofIASTED conference on Circuits, Signals, and Systems, 2006,248–253.
  3. [3] H. Al-Asaad, Efficient global fault collapsing for combinationallibrary modules, Proceedings of the International Conferenceon Computer Design (CDES), 2007, 37–43.
  4. [4] M. Abramovici, M.A. Breuer, & A.D. Friedman, Digital systemstesting and testable design (New York: Computer SciencePress, 1990).
  5. [5] A. Lioy, Advanced fault collapsing, IEEE Design and Test ofComputers, 9 (1), 1992, 64–71.
  6. [6] F. Brglez & H. Fujiwara, A neutral netlist of 10 combinationalbenchmark circuits and a target translator in fortran, Proceed-ings of the International Symposium on Circuits and Systems,1985, 695–698.
  7. [7] A.V.S.S. Prasad, V.D. Agrawal, & M.V. Atre, A new algorithmfor global fault collapsing into equivalence and dominancesets, Proceedings of the International Test Conference, 2002,391–397.
  8. [8] V.D. Agrawal, A.V.S.S. Prasad, & M.V. Atre, Fault collapsingvia functional dominance, Proceedings of the International TestConference, 2003, 274–280.
  9. [9] R. Sandireddy & V.D. Agrawal, Diagnostic and detectionfault collapsing for multiple output circuits, Proceedings of theDesign, Automation and Test in Europe, 2005, 1014–1019.
  10. [10] H. Al-Asaad & R. Lee, Simulation-based approximate globalfault collapsing, Proceedings of the International Conferenceon VLSI, 2002, 72–77.
  11. [11] R. Bryant, Graph-based algorithms for Boolean function ma-nipulation, IEEE Transactions on Computers, C-35 (8), 1986,677–691.
  12. [12] Texas Instruments, The TTL Logic Data Book (Dallas: TexasInstruments, 1988).
  13. [13] H. Al-Asaad & J.P. Hayes, Logic design verification via sim-ulation and automatic test pattern generation, Journal ofElectronic Testing: Theory and Applications, 16 (6), 2000,575–589.
  14. [14] H. Al-Asaad & J.P. Hayes, ESIM: A multimodel design errorand fault simulator for logic circuits, Proceedings of the IEEEVLSI Test Symposium, 2000, 221–228.

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